RISC-V NOELV Virtex Ultrascale+ VCU118 board Design Template
----------------------

The only difference between this design template and the one in noelv-xilinx-vcu118 is
that this design implements 2 GRGPREG modules. These modules can be used to generate
external interrupts and external Resumable Non-Maskable interrupts. The purpose of
these modules is simply to test the interrupts.

These design template has been built in order to instantiate a NOELV core in a Xilinx
Virtex Ultrascale+ VCU118 board.

Information on the VCU118 at:

https://www.xilinx.com/products/boards-and-kits/vcu118.html

---------------------
Design Requirements
---------------------

The design has been tested with the following tools:

Mentor Modelsim 10.6a
Vivado 2020.2

----------------------
Flow
----------------------

* Design structure

All NOEL-V template design are structured in a similar way. The IP core
instantiations are done in the noelvcore.vhd file located in the 
noelv-generic/rtl/core directory and are common for all designs. The "CORE_DIR" 
Makefile variable points to the location of the "rtl/core" directory and can be
changed to point to a local copy if needed. The top-level design (together with
configuration file) is separate for each template design and handles board 
specific things like: different memory controllers, clock and  reset 
implementations, and external interface connections (pad instantiations).

Files are arranged as follow:
config.vhd                  - Design configuration (generated by make xconfig)
rtl/core/                   - Core-level HDL files (where IPs are instantiated, 
  cfgmap.vhd                  shared by other template designs)
  noelvcore.vhd
  rev.vhd
rtl/                        - Top-level HDL files (including board/testbench
  noelvmp.vhd                 specifics: memory controller, ETH PHY, ...)
  ahbrom.vhd
  ahbrom64.vhd
  ahbrom128.vhd
cfg/                        - Extra configuration level (mostly forwarded form
  config_local.vhd            config.vhd)
tb/                         - Testbench
  testbench.vhd
sw/                         - Local system test application
  systest.c
scripts/                    - Scripts, local constraints files


************************
Simulate
************************

* The design does not support DDR4 MIG and GRETH IPs.
* An AHBRAM loaded with the ram.srec image is instantiated only if you opt for the DDR4 memory with the CONFIG_MIG_7SERIES_MODEL variables set to Y. This will instantiate and ahbramsim with the image loaded.
* Default (set in Makefile) is CONFIG_MIG_7SERIES_MODEL=Y

make map_xilinx_7series_lib
make sim
make sim-launch (no ram.srec if on-chip ahbram)

************************
Benchmark
************************

If you would like to perform a benchmark simulation, you first need to compile it and replace the content of ram.srec.

************************
Synthesize
************************

You could launch the Vivado GUI with the following target:

make vivado-launch

If you would like to run in batch mode, then issue the following commands:

make vivado

***********************
Programming the FPGA
***********************
(Using the script doprog.tcl)
make prog-fpga

***********************
Connecting with GRMON
***********************
If connecting to JTAG port and USB cable:
grmon -digilent

If connecting using Xilinx Platform Cable:
grmon -xilusb

If connecting with ethernet:
- first connect with JTAG debug link and source the script eth_test.tcl 
  to bring up the SGMII PHY
- afterwards it will be possible to connect using the ECDL debug link
  grmon -eth 192.168.0.236


***********************
Output form GRMON
***********************

> grmon -eth  192.168.0.236 -u -nb 

  GRMON debug monitor v3.2.13-1-g7ec1290 64-bit internal version
  
  Copyright (C) 2021 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
  This internal version will expire on 02/07/2022

Parsing -eth 192.168.0.236
Parsing -u
Parsing -nb

Commands missing help:

 Ethernet startup...
  Device ID:           0x287
  GRLIB build version: 4267
  Detected frequency:  125.0 MHz
  
  Component                            Vendor
  NOEL-V RISC-V Processor              Cobham Gaisler
  NOEL-V RISC-V Processor              Cobham Gaisler
  NOEL-V RISC-V Processor              Cobham Gaisler
  NOEL-V RISC-V Processor              Cobham Gaisler
  GR Ethernet MAC                      Cobham Gaisler
  AHB-to-AHB Bridge                    Cobham Gaisler
  AHB Debug UART                       Cobham Gaisler
  JTAG Debug Link                      Cobham Gaisler
  EDCL master interface                Cobham Gaisler
  Xilinx MIG Controller                Cobham Gaisler
  Generic AHB ROM                      Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  RISC-V CLINT                         Cobham Gaisler
  RISC-V PLIC                          Cobham Gaisler
  RISC-V Debug Module                  Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  AHB-to-AHB Bridge                    Cobham Gaisler
  AMBA Trace Buffer                    Cobham Gaisler
  Version and Revision Register        Cobham Gaisler
  AHB Status Register                  Cobham Gaisler
  General Purpose I/O port             Cobham Gaisler
  Modular Timer Unit                   Cobham Gaisler
  Generic UART                         Cobham Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys
  cpu0      Cobham Gaisler  NOEL-V RISC-V Processor    
            AHB Master 0
  cpu1      Cobham Gaisler  NOEL-V RISC-V Processor    
            AHB Master 1
  cpu2      Cobham Gaisler  NOEL-V RISC-V Processor    
            AHB Master 2
  cpu3      Cobham Gaisler  NOEL-V RISC-V Processor    
            AHB Master 3
  greth0    Cobham Gaisler  GR Ethernet MAC    
            AHB Master 4
            APB: fc084000 - fc084100
            IRQ: 5
            1000 Mbit capable
            edcl ip 192.168.0.236, buffer 2 kbyte
  ahb2ahb0  Cobham Gaisler  AHB-to-AHB Bridge    
            AHB Master 5
            AHB: ffe00000 - fff00000
            USR: 00000114
            USR: ffe00000
  ahbuart0  Cobham Gaisler  AHB Debug UART    
            AHB Master 0
            APB: fc086000 - fc086100
            Baudrate 115200, AHB frequency 125.00 MHz
  ahbjtag0  Cobham Gaisler  JTAG Debug Link    
            AHB Master 1
  edcl0     Cobham Gaisler  EDCL master interface    
            AHB Master 2
  mig0      Cobham Gaisler  Xilinx MIG Controller    
            AHB: 00000000 - 20000000
            SDRAM: 512 Mbyte
  ahbrom0   Cobham Gaisler  Generic AHB ROM    
            AHB: c0000000 - e0000000
            32-bit ROM: 512 MB @ 0xc0000000
  apbmst0   Cobham Gaisler  AHB/APB Bridge    
            AHB: fc000000 - fc100000
  clint0    Cobham Gaisler  RISC-V CLINT    
            AHB: e0000000 - e0100000
  plic0     Cobham Gaisler  RISC-V PLIC    
            AHB: f8000000 - fc000000
            16 contexts, 32 interrupt sources
  dm0       Cobham Gaisler  RISC-V Debug Module    
            AHB: fe000000 - ff000000
            hart0: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                   ISA A C D F H I M,  Modes M S U
                   Stack pointer 0x1ffffff0
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
                   3 triggers,
                   itrace 64 lines
            hart1: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                   ISA A C D F H I M,  Modes M S U
                   Stack pointer 0x1ffffff0
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
                   3 triggers,
                   itrace 64 lines
            hart2: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                   ISA A C D F H I M,  Modes M S U
                   Stack pointer 0x1ffffff0
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
                   3 triggers,
                   itrace 64 lines
            hart3: DXLEN 64, MXLEN 64, SXLEN 64, UXLEN 64
                   ISA A C D F H I M,  Modes M S U
                   Stack pointer 0x1ffffff0
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
                   3 triggers,
                   itrace 64 lines
  apbmst1   Cobham Gaisler  AHB/APB Bridge    
            AHB: fc000000 - fc100000
  ahb2ahb1  Cobham Gaisler  AHB-to-AHB Bridge    
            AHB: 00000000 - 80000000
            AHB: 80000000 - c0000000
            AHB: c0000000 - e0000000
            AHB: e0000000 - 00000000
            USR: 00000111
            USR: fff00000
  ahbtrace0 Cobham Gaisler  AMBA Trace Buffer    
            AHB: ffe00000 - ffe20000
            Trace buffer size: 128 lines
  version0  Cobham Gaisler  Version and Revision Register    
            APB: fc081000 - fc081100
            Version 0, Revision 110
  ahbstat0  Cobham Gaisler  AHB Status Register    
            APB: fc082000 - fc082100
            IRQ: 4
  gpio0     Cobham Gaisler  General Purpose I/O port    
            APB: fc083000 - fc083100
  gptimer0  Cobham Gaisler  Modular Timer Unit    
            APB: fc000000 - fc000100
            IRQ: 2
            16-bit scalar, 2 * 32-bit timers, divisor 125
  uart0     Cobham Gaisler  Generic UART    
            APB: fc001000 - fc001100
            IRQ: 1            Baudrate 38390, FIFO debug mode available
  
grmon3> q
  

