NOEL-v Versal Alpha Data ADM-PA100 board Design Template
(taken from Generic RISC-V NOEL-V Template Design)
----------------------

* Design structure

All NOEL-V template design are structured in a similar way. The IP core
instantiations are done in the noelvcore.vhd file located in the
noelv-generic/rtl/core directory and are common for all designs. The "CORE_DIR"
Makefile variable points to the location of the "rtl/core" directory and can be
changed to point to a local copy if needed. The top-level design (together with
configuration file) is separate for each template design and handles board
specific things like: different memory controllers, clock and  reset
implementations, and external interface connections (pad instantiations).

Files are arranged as follow:
config.vhd                  - Design configuration (generated by make xconfig)
rtl/core/                   - Core-level HDL files (where IPs are instantiated,
  cfgmap.vhd                  shared by other template designs)
  noelvcore.vhd
  rev.vhd
rtl/                        - Top-level HDL files (including board/testbench
  noelvmp.vhd                 specifics: memory controller, ETH PHY, ...)
  ahbrom.vhd
  ahbrom64.vhd
  ahbrom128.vhd
cfg/                        - Extra configuration level (mostly forwarded form
  config_local.vhd            config.vhd)
tb/                         - Testbench
  testbench.vhd
sw/                         - Local system test application
  systest.c
scripts/                    - Scripts, local constraints files


------------------------------
* Simulate
------------------------------

make soft
make map_xilinx_7series_lib
make sim (compile)
make sim-run (run simulation in batch-mode)
make sim-launch (launch simulator and run simulation)

------------------------------
* Synthesize
------------------------------

The design needs a CIPS block for clocks, reset and JTAG.
This is instantiated in design as an empty component.
The CIPS IP is created as a Block Diagram using Vivado Tcl script (scripts/versal_bd.tcl).

To build the design with Vivado, make sure that Vivado is in the PATH variable and run:

make vivado-launch
(This automatically runs the scripts/versal_bd.tcl script to create the CIPS IP)

If not using Vivado 2025.1, it is necessary to open the Vivado GUI and upgrade the CIPS block manually.

Note that running Vivado in batch mode (make vivado) is currently not supported as it fails
during the implementation phase, despite the fact that synthesis completes successfully.


Program FPGA via Hardware Manager and then close server and connect GRMON.


 GRMON debug monitor v3.3.4 64-bit internal version

  Copyright (C) 2023 Frontgrade Gaisler - All rights reserved.
  For latest updates, go to https://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com

  This internal version will expire on 06/07/2024

Parsing -digilent
Parsing -u
Parsing -nb

Commands missing help:
 echotrace
 package

JTAG chain (2): xcvc1902 zynq7000_arm_dap
WARNING! DRVMGR:  GAISLER_AHBRAM       version 20 (01:00e.14) driver NOT FOUND!   Using version 00
WARNING! DRVMGR:  GAISLER_AHBRAM       version 20 (01:00e.14) driver NOT FOUND!   Using version 00
  Device ID:           0x291
  GRLIB build version: 4283
  Detected frequency:  100.0 MHz

  Component                            Vendor
  NOEL-V RISC-V Processor              Frontgrade Gaisler
  AHB Debug UART                       Frontgrade Gaisler
  JTAG Debug Link                      Frontgrade Gaisler
  AHB/APB Bridge                       Frontgrade Gaisler
  Single-port AHB SRAM module          Frontgrade Gaisler
  Generic AHB ROM                      Frontgrade Gaisler
  RISC-V ACLINT                        Frontgrade Gaisler
  RISC-V PLIC                          Frontgrade Gaisler
  AHB-to-AHB Bridge                    Frontgrade Gaisler
  RISC-V Debug Module                  Frontgrade Gaisler
  Generic UART                         Frontgrade Gaisler
  Modular Timer Unit                   Frontgrade Gaisler
  Version and Revision Register        Frontgrade Gaisler
  AHB Status Register                  Frontgrade Gaisler

  Use command 'info sys' to print a detailed report of attached cores

grmon3> load systest.elf
                 0 .text             91.4kB /  91.4kB   [===============>] 100%
             16da8 .rodata            2.6kB /   2.6kB   [===============>] 100%
             17810 .init_array          8B              [===============>] 100%
             17818 .fini_array          8B              [===============>] 100%
             17820 .data              2.6kB /   2.6kB   [===============>] 100%
             18288 .sdata             288B              [===============>] 100%
             183a8 .eh_frame            4B              [===============>] 100%
  Total size: 96.91kB (181.43kbit/s)
  Entry point 0x00000000
  Image /home/kenneth/proj/git_master/grlib/designs/noelv-ada-adm-pa100/systest.elf loaded

grmon3> run
-----------------------
INF : Systest start.
-----------------------
-----------------------
INF : Systest finished.
-----------------------
  Forced into debug mode
  0x000153b0: 00100073  ebreak  <_exit+0>


------------------------------
* Test application
------------------------------

The simulation boots the code located in prom.srec which then jumps to ram.srec.

Run "make prom.srec" to recompile prom.srec. The source is prom.S located in the
"sw" directory or GRLIB/software/noelv/systest.

Run "make ram.srec" to recompile ram.srec. The source is systest.c located in the
"sw" directory or GRLIB/software/noelv/systest.

To regenerate the AHBROM run "make ahbrom_gen". This will generate ahbrom.vhd,
ahbrom64.vhd, and ahbrom128.vhd form prom.elf (generated for prom.S).

* Debug-Module control

The testbench has a basic Debug-Module control sequence implemented. This is
enabled by setting the dm_ctrl generic to 1. When enabled, the CPU will be halted
after reset. Then the PC is updated and the CPU resume execution.

------------------------------
* Example simulation output
------------------------------

 NOELV/GRLIB Generic Demonstration design
# GRLIB Version 2023.2.0, build 4283
# Target technology: versal    , memory library: versal
# ahbctrl: AHB arbiter/multiplexer rev 1
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte
# ahbctrl: AHB masters: 4, AHB slaves: 9
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte
# ahbctrl: mst0: Frontgrade Gaisler      NOEL-V RISC-V Processor
# ahbctrl: mst2: Frontgrade Gaisler      RISC-V Debug Module
# ahbctrl: slv0: Frontgrade Gaisler      AHB/APB Bridge
# ahbctrl:       memory at 0xfc000000, size 1 Mbyte
# ahbctrl: slv1: Frontgrade Gaisler      Single-port AHB SRAM module
# ahbctrl:       memory at 0x00000000, size 2048 Mbyte, cacheable, prefetch
# ahbctrl: slv2: Frontgrade Gaisler      Single-port AHB SRAM module
# ahbctrl:       memory at 0xc0000000, size 512 Mbyte, cacheable, prefetch
# ahbctrl: slv3: Frontgrade Gaisler      Test report module
# ahbctrl:       memory at 0x80000000, size 1 Mbyte
# ahbctrl: slv5: Frontgrade Gaisler      RISC-V ACLINT
# ahbctrl:       memory at 0xe0000000, size 1 Mbyte
# ahbctrl: slv7: Frontgrade Gaisler      RISC-V PLIC
# ahbctrl:       memory at 0xf8000000, size 64 Mbyte
# ahbctrl: slv8: Frontgrade Gaisler      AHB-to-AHB Bridge
# ahbctrl:       memory at 0xffe00000, size 1 Mbyte
# apbctrl: APB Bridge at 0xfc000000 rev 1
# apbctrl: slv0: Frontgrade Gaisler      Generic UART
# apbctrl:       I/O ports at 0xfc001000, size 256 byte
# apbctrl: slv1: Frontgrade Gaisler      Modular Timer Unit
# apbctrl:       I/O ports at 0xfc000000, size 256 byte
# apbctrl: slv4: Frontgrade Gaisler      Version and Revision Register
# apbctrl:       I/O ports at 0xfc081000, size 256 byte
# apbctrl: slv5: Frontgrade Gaisler      AHB Status Register
# apbctrl:       I/O ports at 0xfc082000, size 256 byte
# apbctrl: slv9: Frontgrade Gaisler      AHB Debug UART
# apbctrl:       I/O ports at 0xfc086000, size 256 byte
# ahbram1: AHB SRAM Module rev 1, 1024 kbytes
# ahbram0: AHB SRAM Module rev 1, 1024 kbytes
# testmod2: Test report module
# grversion1: General Version Number rev 0
# ahbstat2: AHB status unit rev 0, irq 4
# ahbjtag AHB Debug JTAG rev 2
# ahbuart6: AHB Debug UART rev 0
# gptimer8: Timer Unit rev 1, 16-bit scaler, 2 32-bit timers, irq 2
# apbuart7: Generic UART rev 1, fifo 8, irq 1, scaler bits 12
# clkgen_Versal : Unisim.MMCME4_ADV
# clkgen_Versal : clock generator, version 1
# clkgen_Versal : Frequency 300000KHz, DCM divisor 4/12
# noelvsys: NOELV subsystem with 1 cores
# noelvsys: ---------------------------------------------------
# noelvsys:   Debug masters:
# noelvsys:       0 ext#0  AHB Debug UART
# noelvsys:       1 ext#1  JTAG Debug Link
# noelvsys:     WARNING: Debug master 2 seems undriven, check VHDL
# noelvsys:       2 ext#2  Unknown Device
# noelvsys:     WARNING: Debug master 3 seems undriven, check VHDL
# noelvsys:       3 ext#3  Unknown Device
# noelvsys:       4 ext#4  Unknown Device
# noelvsys:   CPU bus masters:
# noelvsys:       0 int    NOEL-V RISC-V Processor
# noelvsys:       1 int    Unknown Device
# noelvsys:       2 int    RISC-V Debug Module
# noelvsys:   CPU bus slaves:
# noelvsys:       0 int    AHB/APB Bridge
# noelvsys:       1 ext#0  Single-port AHB SRAM module
# noelvsys:       2 ext#1  Single-port AHB SRAM module
# noelvsys:       3 ext#2  Test report module
# noelvsys:       4 ext#3  Unknown Device
# noelvsys:       5 int    RISC-V ACLINT
# noelvsys:       6 int    Unknown Device
# noelvsys:       7 int    RISC-V PLIC
# noelvsys:       8 int    AHB-to-AHB Bridge
# noelvsys:   APB bus slaves:
# noelvsys:       0 int    Generic UART
# noelvsys:       1 int    Modular Timer Unit
# noelvsys:       2 int    Unknown Device
# noelvsys:       3 ext#0  Unknown Device
# noelvsys:       4 ext#1  Version and Revision Register
# noelvsys:       5 ext#2  AHB Status Register
# noelvsys:       6 ext#3  Unknown Device
# noelvsys:       7 ext#4  Unknown Device
# noelvsys:       8 ext#5  Unknown Device
# noelvsys:       9 ext#6  AHB Debug UART
# noelvsys: ---------------------------------------------------
# noelvsys:   Memory map:
# noelvsys:     0x00000000-0x7fffffff Single-port AHB SRAM module
# noelvsys:     0x80000000-0x800fffff Test report module
# noelvsys:     0x80100000-0xbfffffff Unmapped AHB space
# noelvsys:     0xc0000000-0xdfffffff Single-port AHB SRAM module
# noelvsys:     0xe0000000-0xe00fffff RISC-V ACLINT
# noelvsys:     0xe0100000-0xf7ffffff Unmapped AHB space
# noelvsys:     0xf8000000-0xfbffffff RISC-V PLIC
# noelvsys:     0xfc000000-0xfc0fffff AHB/APB Bridge
# noelvsys:       0xfc000000-0xfc0000ff Modular Timer Unit
# noelvsys:       0xfc000100-0xfc000fff Unmapped APB space
# noelvsys:       0xfc001000-0xfc0010ff Generic UART
# noelvsys:       0xfc001100-0xfc080fff Unmapped APB space
# noelvsys:       0xfc081000-0xfc0810ff Version and Revision Register
# noelvsys:       0xfc081100-0xfc081fff Unmapped APB space
# noelvsys:       0xfc082000-0xfc0820ff AHB Status Register
# noelvsys:       0xfc082100-0xfc085fff Unmapped APB space
# noelvsys:       0xfc086000-0xfc0860ff AHB Debug UART
# noelvsys:       0xfc086100-0xfc0fffff Unmapped APB space
# noelvsys:     0xfc100000-0xffdfffff Unmapped AHB space
# noelvsys:     0xffe00000-0xffefffff AHB-to-AHB Bridge
# noelvsys:     0xfff00000-0xffffefff Unmapped AHB space
# noelvsys:     0xfffff000-0xffffffff Plug'n'play table
# noelvsys: ---------------------------------------------------
# -----------------------
# INF : Systest start.
# -----------------------
#
# **** GRLIB system test starting ****
# Test passed, halting with IU error mode
#
# ** Failure: Assertion violation.
#    Time: 202818840 ps  Iteration: 9  Process: /testbench/cpu/core0/test0/log File: ./../../lib/gaisler/sim/ahbrep.vhd
# Break in Process log at ./../../lib/gaisler/sim/ahbrep.vhd line 127
